/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/


#ifndef _REGBASE_H
#define _REGBASE_H

#define SPI_CNT     	        (0x1)
#define SMBUS_CNT     	        (0x0)
#define I2C_CNT     	        (0x1)
#define I3C_CNT     	        (0x1)
#define UART_CNT     	        (0x2)

//switch reg addr
#define SW_R5_TCM0_ADDR         (0x20100000)
#define SW_R5_TCM1_ADDR         (0x20110000)
#define SW_R5_TCM2_ADDR         (0x20200000)
#define SW_R5_TCM3_ADDR         (0x20210000)
#define SW_R5_TCM4_ADDR         (0x20300000)
#define SW_R5_TCM5_ADDR         (0x20310000)

#define FLEXRAY0_BASE_ADDR      (0x21790000)
#define FLEXRAY1_BASE_ADDR      (0x21792000)

#define SW_LSP_CRM_ADDR         (0x217A0000)
#define LIN0_BASE_ADDR	        (0x217A1000)
#define LIN1_BASE_ADDR	        (0x217A2000)
#define LIN2_BASE_ADDR	        (0x217A3000)
#define LIN3_BASE_ADDR	        (0x217A4000)
#define LIN4_BASE_ADDR          (0x217A5000)
#define LIN5_BASE_ADDR          (0x217A6000)
#define WDT0_BASE_ADDR          (0x217A7000)
#define WDT1_BASE_ADDR          (0x217A8000)
#define WDT2_BASE_ADDR          (0x217A9000)
#define WDT3_BASE_ADDR          (0x217AA000)
#define WDT4_BASE_ADDR          (0x217AB000)
#define WDT5_BASE_ADDR          (0x217AC000)
#define PWM0_BASE_ADDR          (0x217AD000)
#define MSG_BOX01_ADDR          (0x20120000)
#define MSG_BOX23_ADDR          (0x20220000)
#define MSG_BOX45_ADDR          (0x20320000)

#if defined(CORE0_FLAG) || defined(CORE1_FLAG)
#define MSGBOX_ADDR    MSG_BOX01_ADDR
#elif defined(CORE2_FLAG) || defined(CORE3_FLAG)
#define MSGBOX_ADDR    MSG_BOX23_ADDR
#elif defined(CORE4_FLAG) || defined(CORE5_FLAG)
#define MSGBOX_ADDR    MSG_BOX45_ADDR
#else
    #error "CORE[x]_FLAG need define, x=0/1/2"
#endif

//realtime system addr
#define SW_CRM_ADDR             (0x217B0000)
#define SW_SYS_CTRL_ADDR        (0x217B1000)
#define SW_SP_DMA_ADDR          (0x217B2000)

#define SW_R5_CSR0_ADDR         (0x2187F000)
#define SW_R5_CSR1_ADDR         (0x218BF000)
#define SW_R5_CSR2_ADDR         (0x218FF000)


#define GIC_BASE_ADDR           (0x21700000)

#define SOC_PMM_ADDR            (0x30001000)

#define SPI0_BASE_ADDR          (0xD0005000) //realtime no use
#define I2C0_BASE_ADDR	        (0xC1740000) //safety no use
#define UART0_BASE_ADDR         (0xD0003000)
#define UART1_BASE_ADDR         (0xD0004000)
#define UART2_BASE_ADDR         (0xD0023000)
#define UART3_BASE_ADDR         (0xD0024000)

#define RT_PMM_ADDR             (0xD1035000)

#define SP_DMA0_BASE_ADDR       (0x217B2000)

#define LIN_DMA_BASE_ADDR             (0x217E0000)
#define LIN_SPDMA0_BASE_ADDR            (0x217B2000)
#define LIN_SPDMA1_BASE_ADDR            (0x217B3000)

#define SDMA_BASE_ADDR                          (0x217E0000)

#define TIMER_CFG_CHANNEL_NUM (8)

#define SWITCH_CRM_ADDR         (0x217B0000)
#define SWITCH_SYS_CTRL_ADDR    (0x217B1000)
#define SWITCH_R5_CSR0          (0x2187F000)
#define SWITCH_R5_CSR1          (0x218BF000)
#define SWITCH_R5_CSR2          (0x218FF000)

#define RT_UART0_BASE_ADDR         (0xD0003000)
#define RT_UART1_BASE_ADDR         (0xD0004000)
#define RT_UART2_BASE_ADDR         (0xD0023000)
#define RT_UART3_BASE_ADDR         (0xD0024000)

#define SOC_UART0_BASE_ADDR         (0x20007000)
#define SOC_UART1_BASE_ADDR         (0x20008000)
#define SOC_UART2_BASE_ADDR         (0x20027000)
#define SOC_UART3_BASE_ADDR         (0x20028000)


//***********************crpm & sysctrl reg detail********************//
//CRM clock and reset
#define SAFETY_CRM_ADDR (0xC0030000)

#define SAFETY_RELEASE_CTRL      (SAFETY_CRM_ADDR+0x24)
/*���ܲ��� timer addr*/
#define TIMER0_PWM0_BASE_ADDR    (PWM0_BASE_ADDR)
#define TST_TIMER_ADDR  TIMER0_PWM0_BASE_ADDR
#endif
